Publicación:
Building a Fab on a Chip

cnea.localizacionCentro Atómico Bariloche
cnea.tipodocumentoARTÍCULO CIENTÍFICO
dc.contributor.authorImboden, M.
dc.contributor.authorHan, H.
dc.contributor.authorStark, T.
dc.contributor.authorLowell, E.
dc.contributor.authorChang, J.
dc.contributor.authorPardo, F.
dc.contributor.authorBolle, C.
dc.contributor.authordel Corro, P.G.
dc.contributor.authorBishop, D.J.
dc.contributor.cneaproductorGerencia Física. Departamento Materia Condensada. División Bajas Temperaturas
dc.date.accessioned2024-05-07T13:36:26Z
dc.date.available2024-05-07T13:36:26Z
dc.date.issued2014-00-00
dc.description.abstractSemiconductor fabs are large, complex industrial sites with costs for a single facility approaching $10B. In this paper we discuss the possibility of putting the entire functionality of such a fab onto a single silicon chip. We demonstrate a path forward where, for certain applications, especially at the nanometer scale, one can consider using a single chip approach for building devices with significant potential cost savings. In our approach, we build micro versions of the macro machines one typically finds in a fab, and integrating all the components together. We argue that the technology now exists to allow one to build a Fab on a Chip.
dc.description.institutionalaffiliationFil.: del Corro, P.G. Comisión Nacional de Energía Atómica. Instituto Balseiro; Argentina
dc.description.institutionalaffiliationexternalFil.: Imboden, M. Boston University; Estados Unidos
dc.description.institutionalaffiliationexternalFil.: Han, H. Boston University; Estados Unidos
dc.description.institutionalaffiliationexternalFil.: Stark, T. Boston University; Estados Unidos
dc.description.institutionalaffiliationexternalFil.: Lowell, E. Boston University; Estados Unidos
dc.description.institutionalaffiliationexternalFil.: Chang, J. Boston University; Estados Unidos
dc.description.institutionalaffiliationexternalFil.: Pardo, F. Bell Labs. Alcatel-Lucen; Estados Unidos
dc.description.institutionalaffiliationexternalFil.: Bolle, C. Labs. Alcatel-Lucen; Estados Unidos
dc.description.institutionalaffiliationexternalFil.: Bishop, D.J. Boston University; Estados Unidos
dc.description.recordsetsectionProducción científica
dc.description.recordsetseriesContribución a revistas científicas
dc.format.extent14 p.
dc.identifier.citationNanoscale, 2014, 6, 5049
dc.identifier.doihttp://dx.doi.org/10.1039/C3NR06087J
dc.identifier.issn2040-3372
dc.identifier.urihttps://nuclea.cnea.gob.ar/handle/20.500.12553/5280
dc.language.ISO639-3eng
dc.publisherRoyal Society of Chemistry
dc.relation.ispartofn. 6
dc.relation.ispartofseriesNanoscale
dc.rights.accesslevelinfo:eu-repo/semantics/openAccess
dc.rights.urihttps://creativecommons.org/licenses/by-nc-sa/4.0/
dc.subject.fordCIENCIAS NATURALES
dc.subject.fordCIENCIAS FÍSICAS
dc.subject.inisSILICIO
dc.subject.inisMEMS
dc.subject.keywordSilicon
dc.subject.keywordNanometer scale
dc.subject.keywordMEMS
dc.titleBuilding a Fab on a Chip
dc.typeARTÍCULO
dc.type.openaireinfo:eu-repo/semantics/article
dc.type.snrdinfo:ar-repo/semantics/artículo
dc.type.versioninfo:eu-repo/semantics/publishedVersion
dspace.entity.typePublication

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